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CYRF6936

Document #: 38-16015 Rev. *F Page 7 of 39

Interrupts

The device provides an interrupt (IRQ) output, which is config-

urable to indicate the occurrence of various different events.

The IRQ pin may be programmed to be either active high or

active low, and be either a CMOS or open drain output. A full

description of all the available interrupts can be found in

Section 9.0.

The CYRF6936 IC features three sets of interrupts: transmit,

receive, and system interrupts. These interrupts all share a

single pin (IRQ), but can be independently enabled/disabled.

The contents of the enable registers are preserved when

switching between transmit and receive modes.

If more than one interrupt is enabled at any time, it is

necessary to read the relevant status register to determine

which event caused the IRQ pin to assert. Even when a given

interrupt source is disabled, the status of the condition that

would otherwise cause an interrupt can be determined by

reading the appropriate status register. It is therefore possible

to use the devices without making use of the IRQ pin by polling

the status register(s) to wait for an event, rather than using the

IRQ pin.

Clocks

A 12-MHz crystal (30-ppm or better) is directly connected

between XTAL and GND without the need for external capac-

itors. A digital clock out function is provided, with selectable

output frequencies of 0.75-, 1.5-, 3-, 6-, or 12-MHz. This output

may be used to clock an external microcontroller (MCU) or

ASIC. This output is enabled by default, but may be disabled.

Below are the requirements for the crystal to be directly

connected to XTAL pin and GND:

• Nominal Frequency: 12 MHz

• Operating Mode: Fundamental Mode

• Resonance Mode: Parallel Resonant

• Frequency Initial Stability: ±30 ppm

• Series Resistance: <

60 ohms

• Load Capacitance: 10 pF

• Drive Level: 10 µW–100 µW

Power Management

The operating voltage of the device is 1.8V to 3.6V DC, which

is applied to the V

BAT

pin. The device can be shutdown to a

fully static sleep mode by writing to the FRC END = 1 and END

STATE = 000 bits in the XACT_CFG_ADR register over the

SPI interface. The device will enter sleep mode within 35-µs

after the last SCK positive edge at the end of this SPI trans-

action. Alternatively, the device may be configured to automat-

ically enter sleep mode after completing packet transmission

or reception. When in sleep mode, the on-chip oscillator is

stopped, but the SPI interface remains functional. The device

will wake from sleep mode automatically when the device is

commanded to enter transmit or receive mode. When

resuming from sleep mode, there is a short delay while the

oscillator restarts. The device may be configured to assert the

IRQ pin when the oscillator has stabilized.

The output voltage (V

REG

) of the Power Management Unit

(PMU) is configurable to several minimum values between

2.4V and 2.7V. V

REG

may be used to provide up to 15 mA

(average load) to external devices. It is possible to disable the

PMU, and to provide an externally regulated DC supply

voltage to the device’s main supply in the range 2.4V to 3.6V.

The PMU also provides a regulated 1.8V supply to the logic.

The PMU has been designed to provide high boost efficiency

(74–85% depending on input voltage, output voltage and load)

when using a Schottky diode and power inductor, eliminating

the need for an external boost converter in many systems

where other components require a boosted voltage. However,

reasonable efficiencies (69-82% depending on input voltage,

output voltage and load) may be achieved when using low cost

components such as SOT23 diodes and 0805 inductors.

The PMU also provides a configurable low battery detection

function which may be read over the SPI interface. One of

seven thresholds between 1.8V and 2.7V may be selected.

The interrupt pin may be configured to assert when the voltage

on the V

BAT

pin falls below the configured threshold. LV IRQ

is not a latched event. Battery monitoring is disabled when the

device is in sleep mode.

Low Noise Amplifier (LNA) and Received

Signal Strength Indication (RSSI)

The gain of the receiver may be controlled directly by clearing

the AGC EN bit and writing to the Low Noise Amplifier (LNA)

bit of the RX_CFG_ADR register. When the LNA bit is cleared,

the receiver gain is reduced by approximately 20 dB, allowing

accurate reception of very strong received signals (for

example when operating a receiver very close to the trans-

mitter). Approximately 30 dB of receiver attenuation can be

added by setting the Attenuation (ATT) bit; this allows data

reception to be limited to devices at very short ranges.

Disabling AGC and enabling LNA is recommended unless

receiving from a device using external PA.

When the device is in receive mode the RSSI_ADR register

returns the relative signal strength of the on-channel signal

power.

When receiving, the device will automatically measure and

store the relative strength of the signal being received as a 5-

bit value. An RSSI reading is taken automatically when the

SOP is detected. In addition, a new RSSI reading is taken

every time the previous reading is read from the RSSI_ADR

given channel to be easily measured when RSSI is read when

no signal is being received. A new reading can occur as fast

as once every 12 µs.

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