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CYRF6936

Document #: 38-16015 Rev. *F Page 3 of 39

6.0 Functional Overview

The CYRF6936 IC provides a complete WirelessUSB SPI to

antenna wireless MODEM. The SoC is designed to implement

wireless device links operating in the worldwide 2.4-GHz ISM

frequency band. It is intended for systems compliant with

world-wide regulations covered by ETSI EN 301 489-1 V1.41,

ETSI EN 300 328-1 V1.3.1 (Europe), FCC CFR 47 Part 15

(USA and Industry Canada) and TELEC ARIB_T66_March,

2003 (Japan).

The SoC contains a 2.4-GHz 1-Mbps GFSK radio transceiver,

packet data buffering, packet framer, DSSS baseband

controller, Received Signal Strength Indication (RSSI), and

SPI interface for data transfer and device configuration.

The radio supports 98 discrete 1-MHz channels (regulations

may limit the use of some of these channels in certain jurisdic-

tions).

The baseband performs DSSS spreading/despreading, Start

of Packet (SOP), End of Packet (EOP) detection and CRC16

generation and checking. The baseband may also be

configured to automatically transmit Acknowledge (ACK)

handshake packets whenever a valid packet is received.

When in receive mode, with packet framing enabled, the

device is always ready to receive data transmitted at any of the

supported bit rates enabling the implementation of mixed-rate

systems in which different devices use different data rates.

This also enables the implementation of dynamic data rate

systems, which use high data rates at shorter distances and/or

in a low-moderate interference environment, and change to

lower data rates at longer distances and/or in high interference

environments.

In addition, the CYRF6936 IC has a Power Management Unit

(PMU) which allows direct connection of the device to any

battery voltage in the range 1.8V to 3.6V. The PMU conditions

the battery voltage to provide the supply voltages required by

the device, and may supply external devices.

Data Transmission Modes

The SoC supports four different data transmission modes:

• In GFSK mode, data is transmitted at 1 Mbps, without any

DSSS.

• In 8DR mode, 8 bits are encoded in each derived code

symbol transmitted.

• In DDR mode, 2-bits are encoded in each derived code

symbol transmitted. (As in the CYWUSB6934 DDR mode).

• In SDR mode, 1 bit is encoded in each derived code symbol

transmitted. (As in the CYWUSB6934 standard modes.)

Both 64-chip and 32-chip Pseudo-Noise (PN) Codes are

supported. The four data transmission modes apply to the data

after the SOP. In particular the length, data, and CRC16 are all

sent in the same mode. In general, lower data rates reduce

packet error rate in any given environment.

Link Layer Modes

The CYRF6936 IC device supports the following data packet

framing features:

SOP – Packets begin with a 2-symbol Start of Packet (SOP)

marker. This is required in GFSK and 8DR modes, but is

optional in DDR mode and is not supported in SDR mode; if

framing is disabled then an SOP event is inferred whenever

two successive correlations are detected. The

SOP_CODE_ADR code used for the SOP is different from that

used for the “body” of the packet, and if desired may be a

different length. SOP must be configured to be the same

length on both sides of the link.

Length – There are two options for detecting the end of a

packet. If SOP is enabled, then the length field should be

enabled. GFSK and 8DR must enable the length field. This is

the first 8-bits after the SOP symbol, and is transmitted at the

payload data rate. When the length field is enabled, an End of

Packet (EOP) condition is inferred after reception of the

number of bytes defined in the length field, plus two bytes for

the CRC16 (when enabled—see below). The alternative to

using the length field is to infer an EOP condition from a config-

urable number of successive non-correlations; this option is

not available in GFSK mode and is only recommended to

enable when using SDR mode.

CRC16 – The device may be configured to append a 16-bit

CRC16 to each packet. The CRC16 uses the USB CRC

polynomial with the added programmability of the seed. If

enabled, the receiver will verify the calculated CRC16 for the

payload data against the received value in the CRC16 field.

The seed value for the CRC16 calculation is configurable, and

the CRC16 transmitted may be calculated using either the

loaded seed value or a zero seed; the received data CRC16

will be checked against both the configured and zero CRC16

seeds.

CRC16 detects the following errors:

• Any one bit in error

• Any two bits in error (no matter how far apart, which column,

and so on)

• Any odd number of bits in error (no matter where they are)

• An error burst as wide as the checksum itself

Figure 6-1 shows an example packet with SOP, CRC16 and

lengths fields enabled, and Figure 6-2 shows a standard ACK

packet.

Figure 6-1. Example Packet Format

P SOP 1 SOP 2 Length CRC 16

Payload Data

Preamble

n x 16us

1st Framing

Symbol*

2nd Framing

Symbol*

Packet

length

1 Byte

Period

*Note:32 or 64us

1 2 3 4 5 6 7 8 ... 38 39

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